1. Field of the Invention
This invention relates to a semiconductor device, and particularly to a semiconductor device suitable for use in a power FET that handles a high-frequency signal.
2. Description of the Related Art
As a technique related to this type of FET, one described in the following reference, for example, has heretofore been known.
Reference: John L. B. Valker, "High Power GaAs FET Amplifier", ARTECH HOUSE, INC., P. 123, 1993.
FIG. 3 is a pattern plan view showing an example of a chip cl having one configuration of a conventional power FET described in the above-described reference.
This type of FET comprises a region F1 activated as the FET, a row D11-D16 of pads used to draw drain terminals, and a row G11-G14, S11-S15 of pads used to draw gate and source terminals.
The pads for the drains are arranged at uniform intervals as shown in the drawing. Further, the pads for the gates and sources are also alternately placed at uniform intervals.
The conventional power FET has a drawback in that it oscillates at a frequency dependent on the size of the interval between the pads upon its operation.
This drawback will be explained below. In the conventional power FET, the drain pads used as the same terminals exist in plural form as shown in FIG. 3.
This is because there is a restriction on the amount of power capable of being drawn at any one pad. In order to set power quantities capable of being drawn at the respective pads as uniformly as possible or for convenience of the formation of patterns, the intervals between the adjacent pads have heretofore been rendered uniform as shown in FIG. 3 in consideration of workability or the like at wire-bonding. The same signals, i.e., signals identical in amplitude and phase to each other, are supplied to the plurality of pads for the drains. However, since the intervals between the pads are uniform, standing waves in which the positions of the pads are set as nodes, can exist.
Thus, oscillations are likely to take place at a frequency at which the interval between the pads is set to one or half wavelength. The oscillations are likely to occur even in the case of the pad row of the sources and gates.
As has been described above, the conventional power FET has a drawback in that the oscillations take place at the frequency at which the interval between the pads is set to one or half wavelength.